library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.cpu_utils.all;



entity sp is
	generic (
		pins : integer := 10;
		Tpd : Time := unit_delay);
	port (
		clock : in bit;
		clear : in bit;
		inc : in bit;
		dec : in bit;
		spV: out bit;
		q : out bit_vector(pins-1 downto 0)		
	);
end sp;

architecture sp_arh of sp is
	shared variable data: integer range 0 to 2**pins - 1 := 0;
begin

	process(inc, dec, clear)
	begin
		
					
	end process;

	process(clock, inc, dec, clear)
	begin
		if(clock'event and clock='1') then
			--setting spV bit --stack overflow/underflow
			if(clear='1')then spV<='0'after Tpd;
			elsif 	( 
						(inc = '1' and 
						(to_bits(data, pins)(0)='1' and to_bits(data, pins)(1)='1' ))
						and ((to_bits(data, pins)(2)='1' and to_bits(data, pins)(3)='1') 
						and (to_bits(data, pins)(4)='1' and to_bits(data, pins)(5)='1')) 
						and ((to_bits(data, pins)(6)='1' and to_bits(data, pins)(7)='1') 
						and (to_bits(data, pins)(8)='1' and to_bits(data, pins)(9)='1'))
					) 
						or 
					(
						(dec = '1' and 
						(to_bits(data, pins)(0)='0' and to_bits(data, pins)(1)='0')) 
						and ((to_bits(data, pins)(2)='0' and to_bits(data, pins)(3)='0') 
						and (to_bits(data, pins)(4)='0' and to_bits(data, pins)(5)='0'))
						and ((to_bits(data, pins)(6)='0' and to_bits(data, pins)(7)='0') 
						and (to_bits(data, pins)(8)='0' and to_bits(data, pins)(9)='0'))
					)
			then spV <= '1' after Tpd;
			end if;
			
					--update sp value
			if clear = '1' then data := 0;
				else
					if(inc='1')
					then	data := data + 1;
					elsif (dec='1') then data := data - 1;	
					end if; 
				end if;
			q<= to_bits(data,10) after Tpd;
		end if;
	end process;
end sp_arh;